De Souza M.Paz B.C.Flandre D.Pavanello M.A.2019-08-192019-08-192013DE SOUZA, Michelly; PAZ, Bruna Cardoso; FLANDRE, Denis; Pavanello, Marcelo Antonio. Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs. Microelectronics and Reliability, v. 53, p. 848-855, 2013.0026-2714https://repositorio.fei.edu.br/handle/FEI/1098In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried out through experimental measurements of Common-source, Cascode and Wilson current mirrors architectures. The advantages of the use of graded-channel transistors for implementation of current mirrors in comparison to standard ones is discussed, focusing on the increase of output swing and output resistance. In all architectures some performance degradation has been observed with the temperature reduction, although current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. Two-dimensional numerical simulations were performed in order to further investigate the behavior of graded-channel current mirrors, looking at the bias condition of each transistor in the current mirror architectures. The obtained results indicate that good performance, compared to that of GC current mirrors, may be obtained by combining both standard and graded-channel transistors, rather than using the same channel engineering for all devices in the circuit. © 2013 Elsevier Ltd. All rights reserved.Acesso RestritoArtigo10.1016/j.microrel.2013.03.005