Tambara L.A.Kastensmidt F.L.Rech P.Lins F.Medina N.H.Added N.Aguiar V.A.P.Silveira M.A.G.2019-08-192019-08-192018TAMBARA, LUCAS ANTUNES; KASTENSMIDT, FERNANDA LIMA; RECH, PAOLO; LINS, FILIPE; MEDINA, NILBERTO H.; ADDED, NEMITALA; AGUIAR, VITOR A. P.; SILVEIRA, MARCILEI A. G.. Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-based APSoCs. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v. 65, n. 8, p. 1935-1942, 2018.0018-9499https://repositorio.fei.edu.br/handle/FEI/1475© 1963-2012 IEEE.All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system's susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.Acesso RestritoArtigo10.1109/TNS.2018.2844250All programmable system-on-chip (APSoC)fault injection (FI)field-programmable gate array (FPGA)hardware and software co-designprocessorsingle-event effectssoft errors