Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

Rodrido DoriaFLANDRE, D.TREVISOLLI, R.Michelly De SouzaMarcelo Antonio Pavanello2022-01-122022-01-122015-10-13DORIA, R.; FLANDRE, D.; TREVISOLLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.https://repositorio.fei.edu.br/handle/FEI/3953This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.Acesso RestritoUse of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structuresArtigo de evento10.1109/SBMicro.2015.7298134Self-CascodeSilicon-on-InsulatorUTBB