AVILA HERRERA, F.CERDEIRA, A.ESTRADA, M.PAZ, B. C.Marcelo Antonio Pavallo2022-01-122022-01-122016-01-29AVILA HERRERA, F.; CERDEIRA, A.; ESTRADA, M.; PAZ, B. C.; PAVANELLO, M. A. Proposal of compact analytical modeling for trigate junctionless nanowire transistors. 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015, Jan., 2015.https://repositorio.fei.edu.br/handle/FEI/3916A compact analytical model for junctionless nanowire transistors is developed taking into account the fin height and including its capacitance. This model is based on a previous one for double-gate transistors just considering the dependence of the fin height and the short channel effects. The validation has been performed by 3D simulations for structures of 15 nm and 10 nm of height obtaining a very good agreement between modeled and simulated data.Acesso RestritoArtigo de evento10.1109/ROPEC.2015.7395131fin height capacitanceJLTJunctionless nanowire transistor model