Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors

Rodrido DoriaTREVISOLI, R.Michelly De SouzaMarcelo Antonio PavanelloFLANDRE, D.2022-01-122022-01-122017-10-10DORIA, T.; DE SOUZA, M.; PAVANELLO, M. A.; FLANDRÉ, D. Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors. 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016. oCT. 2016.https://repositorio.fei.edu.br/handle/FEI/3853This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.Acesso RestritoUse of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrorsArtigo de evento10.1109/S3S.2016.7804387Active Substrate BiasAnalog BehaviorSelf-Cascode StructureUTBB SOI