Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

TREVISOLI, R DDORIA, R. T.DE SOUZA, MichellyDAS, SamareshFERAIN, I.PAVANELLO, Marcelo A.2019-08-192019-08-192012TREVISOLI, R D; DORIA, R. T.; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, I.; PAVANELLO, Marcelo A.. Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE Transactions on Electron Devices, v. 59, n. 12, p. 3510-3518, 2012.0018-9383https://repositorio.fei.edu.br/handle/FEI/1097Acesso RestritoSurface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire TransistorsArtigo10.1109/TEd.2012.2219055