Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias

Rodrido DoriaTREVISOLI, R.Michelly De SouzaMarcelo Antonio PavanelloFLANDRE, D.2022-01-122022-01-122015-11-20DORIA, R.; TREVISOLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Nov. 2015.https://repositorio.fei.edu.br/handle/FEI/3946This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.Acesso RestritoAnalog performance improvement of self-cascode structures composed by UTBB transistors using back gate biasArtigo de evento10.1109/S3S.2015.7333512Active Substrate BiasAnalog BehaviorSelf-Cascode StructureUTBB SOI