ASSALTI, R.Marcelo Antonio PavanelloMichelly DE SouzaFLANDRE, D.2022-01-122022-01-122014-01-20ASSALTI, R.; PAVANELLO, M. A.; DE SOUZA, M.; FLANDRE, D. Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors. 2014 International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2014 - Conference Proceedings. Jan. 2014.https://repositorio.fei.edu.br/handle/FEI/4021This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.Acesso RestritoArtigo de evento10.1109/ICCDCS.2014.7016159Analog parametersGraded-Channelintrinsic voltage gainSOI nMOSFETtechnological parameters