Drain current and short channel effects modeling in junctionless nanowire transistors

Creative Commons "Este é um artigo publicado em acesso aberto sob uma licença" Creative commons (CC BY 4.0). Fonte: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84899958318&origin=inward. Disponível em: 29 fev. 2024.TREVISOLI, R. D.Rodrigo DoriaMichelly De SouzaMarcelo Antonio Pavanello2023-08-262023-08-262013-01-05TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current and short channel effects modeling in junctionless nanowire transistors. Journal of Integrated Circuits and Systems, v. 8, n. 2, 2013.1872-0234https://repositorio.fei.edu.br/handle/FEI/4949© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.Acesso RestritoDrain current and short channel effects modeling in junctionless nanowire transistorsArtigoAnalytical modelDrain induced barrier loweringJunctionless nanowire transistorsSubthreshold slope