ASSALTI, R.Michelly De SouzaCASSE, M.BARRAUD, S.REIMBOLD, G.VINET, M.FAYNOT, O.2022-01-122022-01-122017-06-29ASSALTI, R.; DE SOUZA, M.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, p. 83-86, jun. 2017.https://repositorio.fei.edu.br/handle/FEI/3838© 2017 IEEE.In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated.Acesso RestritoArtigo de evento10.1109/ULIS.2017.7962607analog performanceasymmetric self-cascodeback gate voltagechannel widthsilicon nanowire