NEMER, J. P.Michelly De SouzaFLANDRE, D.Marcelo Antonio Pavanello2022-01-122022-01-122013-05-16NEMER, J. P.; DE SOUZA, M.; FLANDRE, D.; PAVANELLO, M. A. Analog behavior of submicron graded-Channel SOI MOSFETs varying the channel length, doping concentration and temperature. ECS Transactions, v. 53, n. 5, p. 149-154, Mayo, 2013.1938-5862https://repositorio.fei.edu.br/handle/FEI/4061In this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature. © The Electrochemical Society.Acesso RestritoArtigo de evento10.1149/05305.0149ecst