Browsing by Author FLANDRE, D.
Showing results 1 to 6 of 6
| Issue Date | Title | Author(s) |
| 2017 | An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models | PEREIRA, A. S. N.; STREEL, G.; PLANES, N.; HAOND, M.; GIACOMINI, R.; FLANDRE, D.; KILCHYTSKA, V. |
| 2017 | Effect of the Back Bias on the Analog Performance of Standard FD and UTBB Transistors-Based Self-Cascode Structures | DORIA, R.T.; FLANDRE, D.; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A. |
| 2016 | Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature | Pavanello, Marcelo Antonio; SOUZA, Michelly de; RIBEIRO, Thales Augusto; MARTINO, João Antonio; FLANDRE, D. |
| 2016 | Junctionless nanowire transistors operation at temperatures down to 4.2 K | TREVISOLI, RENAN; SOUZA, Michelly de; DORIA, Rodrigo Trevisoli; KILCHYTSKA, V.; FLANDRE, D.; Pavanello, Marcelo Antonio |
| 2013 | Operation of Lateral SOI PIN Photodiodes with Back-Gate Bias and Intrinsic Length Variation | NOVO, C.; GIACOMINI, R.; AFZALIAN, A.; FLANDRE, D. |
| 2014 | Using diamond layout style to boost MOSFET frequency response of analogue IC | GIMENEZ, S.P.; RENAUX, C.; LEONI, R.D.; FLANDRE, D. |
