Browsing by Author DE SOUZA, Michelly

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing results 1 to 20 of 35  next >
Issue DateTitleAuthor(s)
2008Advantages of Graded-Channel SOI nMOSFETs for Application as Source-Follower Analog BufferDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2011An explicit multi-exponential model for semiconductor junctions with series and shunt resistancesLugo-Muñoz, Denise; MUCI, Juan; ORTIZ-CONDE, Adelmo; García-Sánchez, Francisco J.; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; Pavanello, Marcelo A.
2011Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic DistortionDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2009Analysis of Source Follower Buffers Implemented with Graded-Channel SOI nMOSFETs Operating at Cryogenic TemperaturesDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2012Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETsPAVANELLO, Marcelo A.; DE SOUZA, Michelly; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor
2017Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterizationDORIA, Rodrigo Trevisoli; TREVISOLI, Renan D.; DE SOUZA, Michelly; VINET, MAUD; BARRAUD, SYLVAIN; PAVANELLO, Marcelo A.
2016Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire TransistorsTREVISOLI, RENAN; Doria, Rodrigo Trevisoli; DE SOUZA, Michelly; BARRAUD, SYLVAIN; VINET, MAUD; Pavanello, Marcelo Antonio
2013Approximate analytical expression for the tersminal voltage in multi-exponential diode modelsORTIZ-CONDE, Adelmo; GARCIA-SANCHEZ, Francisco; BARRIOS, Alberto Terán; MUCI, Juan; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2013Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETsDE SOUZA, Michelly; PAZ, Bruna Cardoso; FLANDRE, Denis; Pavanello, Marcelo Antonio
2007Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFETsDE SOUZA, Michelly; PAVANELLO, Marcelo A.
2013Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless TransistorsCERDEIRA, Antonio; CUETO, Magali Estrada; INIGUEZ, Benjamin; TREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2005A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulationDE SOUZA, Michelly; PAVANELLO, Marcelo A.; INIGUEZ, Benjamin; FLANDRE, Denis
2014Compact core model for Symmetric Double-Gate Junctionless TransistorsCERDEIRA, Antonio; AVILA, F.; INIGUEZ, Benjamin; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; CUETO, Magali Estrada
2011Cryogenic Operation of Junctionless Nanowire TransistorDE SOUZA, Michelly; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; TREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; COLINGE, J. -P.
2017Effect of the Back Bias on the Analog Performance of Standard FD and UTBB Transistors-Based Self-Cascode StructuresDORIA, R.T.; FLANDRE, D.; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.
2016Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistorsASSALTI, R.; D'OLIVEIRA, L. M.; PAVANELLO, M. A.; FLANDRE, Denis; DE SOUZA, Michelly
2015Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire TransistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2011Junctionless Multiple-Gate Transistors for Analog ApplicationsDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2019Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current MeasurementsTREVISOLI, Renan D.; DORIA, R. T.; DE SOUZA, Michelly; BARRAUD, S.; PAVANELLO, M. A.
2014Low-Frequency Noise and Effective Trap Density of Short Channel P- and N-Types Junctionless Nanowire TransistorsDORIA, Rodrigo Trevisoli; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.