Browsing by Author DORIA, R. T.

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Showing results 1 to 8 of 8
Issue DateTitleAuthor(s)
2011Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic DistortionDORIA, R. T.; YU, R.; KRANTI, A.; COLINGE, J. P.; PAVANELLO, M. A.; TREVISOLI, R D; SOUZA, M.; LEE, C. W.; FERAIN, I.; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2012Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the TemperatureDORIA, R. T.; TREVISOLI, R D; DE SOUZA, M.; PAVANELLO, M. A.
2019Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current MeasurementsTREVISOLI, Renan D.; DORIA, R. T.; DE SOUZA, Michelly; BARRAUD, S.; PAVANELLO, M. A.
2017A New Method for Series Resistance Extraction of Nanometer MOSFETsTREVISOLI, R.; PAVANELLO, M. A.; DORIA, R. T.; DE SOUZA, M.; BARRAUD, S.; VINET, M.; CASSE, M.; REIMBOLD, G.; FAYNOT, O.; GHIBAUDO, G.
2012Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire TransistorsTREVISOLI, R D; DORIA, R. T.; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, I.; PAVANELLO, Marcelo A.
2012Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire TransistorsTREVISOLI, R D; DORIA, R. T.; DE SOUZA, M.; DAS, S; FERAIN, I.; PAVANELLO, M. A.
2014The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear RegimeDORIA, R. T.; TREVISOLI, R.; DE SOUZA, M.; ESTRADA, M.; CERDEIRA, A.; PAVANELLO, M. A.
2013Trap density characterization through low-frequency noise in junctionless transistorsDORIA, R. T.; TREVISOLI, Renan Doria; DE SOUZA, Michelly; Pavanello, Marcelo Antonio