Browsing by Author PAVANELLO, M. A.

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Showing results 1 to 14 of 14
Issue DateTitleAuthor(s)
20113D simulation of triple-gate MOSFETs with different mobility regionsCONDE, Jorge; CERDEIRA, Antonio; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; KILCHYTSKA, V.; FLANDRE, Denis
2011Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic DistortionDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2011Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic DistortionDORIA, R. T.; YU, R.; KRANTI, A.; COLINGE, J. P.; PAVANELLO, M. A.; TREVISOLI, R D; SOUZA, M.; LEE, C. W.; FERAIN, I.; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2011Cryogenic Operation of Junctionless Nanowire TransistorDE SOUZA, Michelly; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; TREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; COLINGE, J. -P.
2017Effect of the Back Bias on the Analog Performance of Standard FD and UTBB Transistors-Based Self-Cascode StructuresDORIA, R.T.; FLANDRE, D.; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.
2006Evaluation of Graded-Channel SOI MOSFET operation at high temperatureGALETI, M.;Galeti, M;GALETI, MILENE; MARTINO, J. A.; PAVANELLO, M. A.
2016Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistorsASSALTI, R.; D'OLIVEIRA, L. M.; PAVANELLO, M. A.; FLANDRE, Denis; DE SOUZA, Michelly
2011Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETSDORIA, Rodrigo Trevisoli; SIMOEN, Eddy; CLAEYS, Cor; MARTINO, João Antonio; PAVANELLO, Marcelo A.; PAVANELLO, M. A.
2012Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the TemperatureDORIA, R. T.; TREVISOLI, R D; DE SOUZA, M.; PAVANELLO, M. A.
2019Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current MeasurementsTREVISOLI, Renan D.; DORIA, R. T.; DE SOUZA, Michelly; BARRAUD, S.; PAVANELLO, M. A.
2014Low-Frequency Noise and Effective Trap Density of Short Channel P- and N-Types Junctionless Nanowire TransistorsDORIA, Rodrigo Trevisoli; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.
2017A New Method for Series Resistance Extraction of Nanometer MOSFETsTREVISOLI, R.; PAVANELLO, M. A.; DORIA, R. T.; DE SOUZA, M.; BARRAUD, S.; VINET, M.; CASSE, M.; REIMBOLD, G.; FAYNOT, O.; GHIBAUDO, G.
2012Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire TransistorsTREVISOLI, R D; DORIA, R. T.; DE SOUZA, M.; DAS, S; FERAIN, I.; PAVANELLO, M. A.
2014The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear RegimeDORIA, R. T.; TREVISOLI, R.; DE SOUZA, M.; ESTRADA, M.; CERDEIRA, A.; PAVANELLO, M. A.