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Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
(2010-09-05) CONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; Marcelo Antonio Pavanello
The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion
(2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.
This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
Boosting the MOSFETs matching by using diamond layout style
(2017-04-05) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador Gimenez
© 2017, Brazilian Microelectronics Society. All rights reserved.This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.
Origin of the low-frequency noise in the asymmetric self-cascode structure composed by fully depleted SOI nMOSFETs
(2017-08-05) ASSALTI, R.; Rodrigo Doria; FLANDRE, D.; Michelly De Souza
© 2017, Brazilian Microelectronics Society. All rights reserved.In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.

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