Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Comparative study between conventional and wave planar power mosfets(2021-08-27) SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.One of most challenges of nanoelectronics area is to further increase the integration capacity and electrical performance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs). Several approaches have been done to reach this challenges, as for instance, the use of different fabrication processes, new transistors structures (bi and tridimensional), new materials etc. An alternative strategy, in which it is capable of reducing the total die area, mainly of the analog Complementary MOS (CMOS) integrated circuits (ICs), without affecting their electrical performance, is the use non-standard gate geometries (Diamond, Octo, Ellipsoidal, Fish, Wave etc.) for MOSFETs, instead of the rectangular one commonly used today. Previous studies have shown that by using Wave MOSFETs as a basic cell of the Planar Power MOSFETs (PPM) was able to reduce their total die areas. Therefore, the motivation of this paper is to verify by experimental data, the electrical behavior of PPM implemented with Wave layout style in relation to the one of PPM layouted with the conventional rectangular MOSFETs. The CMOS ICs technology used to manufacture these devices was of 350nm-ON Semiconductor. The main finding of this work is that the Wave MOSFET used as a base cell of a PPM (Wave PPM) present a similar electrical characteristics, but it is responsible to reduce in 9.7% its die area in comparison to the one found in PPM layouted with conventional MOSFETs and therefore, the Wave layout style is an alternative layout to reduce the total die area of PPM. c2021 IEEE.
- The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs(2021-08-27) GALEMBECK, E.H. S.; SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.This article describes, for the first time, the study of electrical behavior of the first element belonging to the family of Second Generation of layout styles for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), entitled Half-Diamond. It was conceived in order to further boosting the electrical performance of the analog MOSFETs in relation to the one found in Diamond MOSFETs (hexagonal gate shape). This innovative layout style has by objective further enhance the Longitudinal Corner Effect (LCE) and mainly the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) by the means of further reducing of the effective channel lengths of Diamond MOSFETs in relation to those measured in the conventional (rectangular gate geometry) ones (RMs). The main results found by the three-dimensional numerical simulations indicates that the Half-Diamond MOSFET (HDM) is able to provide a saturation drain current 13% higher than the one observed in the RM counterpart. Furthermore, the electrical behaviors of LCE, PAMDLE and DEPAMBRE in HDM are analyzed in detail by observing the electrical behavior of the electrostatic potentials, longitudinal electric fields and drain current densities. c2021 IEEE.