Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET(2022-08-22) DE LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GALEMBECK, E. H. S.; Salvador Gimenez; CAMILO, L. M.© 2022 IEEE.The zero temperature coefficient (ZTC) is investigated by the simple model and three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectangular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC) technology. A simple model is used to study the behavior of the gate voltage at ZTC (VZTC) in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for EM and CM devices. The VZTC changes in the temperature range investigated showed a temperature mobility degradation dependence and the both devices showed the same behavior. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with 3D simulations results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region.
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.