Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K(2017) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.
- The low-frequency noise behaviour of graded-channel SOI nMOSFETs(2007) Simoen E.; Claeys C.; Chung T.M.; Flandre D.; Pavanello M.A.; Martino J.A.; Raskin J.-P.It is shown that the low-frequency noise in graded-channel (GC) SOI nMOSFETs is generally of the flicker or 1/f noise type. The corresponding input-referred noise spectral density is markedly higher than for the conventional uniformly doped or the intrinsic un-doped fully depleted n-channel SOI transistors. However, this increase can only be partially explained by the effective channel length reduction provided by the lightly doped region of the GC structure. It is furthermore demonstrated that the underlying noise mechanism for the GC structures is rather related to carrier number fluctuations compared with mobility fluctuations for the intrinsic or the uniformly doped fully depleted device. It is concluded that for optimal analog performance of GC SOI nMOSFETs, high gain has to be traded off for higher 1/f noise. © 2007 Elsevier Ltd. All rights reserved.