Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors(2019-08-30) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2019 IEEE.The goal of this work is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with the application of a selected set of back gate biases (VSUB) through DC and AC simulations. A set of different ground planes (GP) arrangements has been considered. It has been shown that the degradation due to the substrate effects increases as the substrate bias is reduced. According to the analysis, it could be observed the GP type influences the capacitive coupling of the structure as the back gate bias is varied. Additionally, it has been shown that the presence of the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the device.
- Effect of substrate bias and temperature variation in the capacitive coupling of soi utbb mosfets(2021-08-23) DA SILVA, E. M.; TREVISOLI, R.; Rodrido Doria© 2021, Brazilian Microelectronics Society. All rights reserved.In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations calibrated to experimental data. The impact of the substrate bias is observed for a set of values ranging from-3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with n-and ptype ground planes (GP-P and GP-N) and without GP have been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.
- Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors(2020-05-26) COSTA, F. J.; DORIA, R. T.; Rodrigo Trevisoli DoriaThe main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.