Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Impact of halo implantation on the lifetime assessment in partially depleted soi transistors(2006-11-03) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 μm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions. In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2μm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range. copyright The Electrochemical Society.
- Effect of substrate bias and temperature variation in the capacitive coupling of soi utbb mosfets(2021-08-23) DA SILVA, E. M.; TREVISOLI, R.; Rodrido Doria© 2021, Brazilian Microelectronics Society. All rights reserved.In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations calibrated to experimental data. The impact of the substrate bias is observed for a set of values ranging from-3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with n-and ptype ground planes (GP-P and GP-N) and without GP have been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.