Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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2 resultados
Resultados da Pesquisa
- Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions(2021-01-05) GONZALEZ, C. J.; MACHADO, D. N.; VAZ, R. G.; VILAS BOAS, A. C.; GONLALEZ, O. L.; PUCHNER, H.; ADDED, N.; MACCHIONE, E. L. A.; AGUIAR, V. A. P.; KASTENSMIDT, F. L.; MEDINA, N. H.; Marcilei Aparecida Guazzelli; BALEN, T. R.© 2021, Brazilian Microelectronics Society. All rights reserved.— This work presents results of three distinct radiation tests performed upon a fault tolerant data acquisition system comprising a design diversity redundancy technique. The first and second experiments are Total Ionizing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based vot-ers, besides additional software and hardware resources used for controlling, monitoring and memory manage-ment. The applied Diversity Triple Modular Redundancy (DTMR) technique, comprises different levels of diversity (temporal and architectural). The circuit was designed in a programmable System-on-Chip (PSoC), fabricated in a 130nm CMOS technology process. Results show that the technique may increase the lifetime of the system under TID if comparing with a non-redundant implementation. Considering the heavy ions experiments the system was proved effective to tolerate 100% of the observed errors originated in the converters, while errors in the processing unit present a higher criticality. Critical errors occur-ring in one of the voters were also observed. A second heavy ion campaign was then carried out to investigate the voters reliability, comparing the the dynamic cross section of three different software-based voter schemes im-plemented in the considered PSoC.
- Robust convolutional neural networks in sram-based fpgas: A case study in image classification(2021-08-23) BENEVENUTI, F.; KASTENSMIDT, F.; OLIVEIRA, A.; ADDED, N.; AGUIAR, V.; MEDINA, N.; Marcilei Aparecida Guazzelli© 2021, Brazilian Microelectronics Society. All rights reserved.— This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.