Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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5 resultados
Resultados da Pesquisa
- Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems(2023-06-20) BALEN, T. R.; GONZALEZ, C. J.; OLIVEIRA, I. F. V.; DA ROSA JR. L. S.; SOARES, R. I.; SCHVITTZ, R. B.; ADDED, N.; MACCHIONE, E. L. A.; AGUIAR, V. A. P.; Marcilei Aparecida Guazzelli; MEDINA, N. H.; BUTZEN, P. F.© 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.This work presents a study on the reliability of voters for approximate fault tolerant systems in the context of single event effects and electromagnetic interference. A first case study analyses different topologies of single-bit majority voters for logic circuits employing fault injection by simulation. In these simulations, an analysis is first performed to identify the critical diffusion areas of the physical implementation according to the voter input vector. Additionally, as a second case study, practical heavy ion experiments on different architectures of software-based approximate voters for mixed-signal applications are also presented, and the cross section of each voter is evaluated. The system comprising the voters was irradiated in two distinct experiments with an 16O ion beam, producing an effective LET at the active region of 5.5 MeV/mg/cm 2 . As a complementary study, a conducted electromagnetic interference injection was also performed, considering two distinct voting schemes. Results of the case-studies allow identifying the most tolerant voter architectures (among the studied ones) for approximate computing applications under single event effects and electromagnetic interference.
- Heavy-Ion-Induced Avalanche Multiplication in Low-Voltage Power VDMosfet(2021-09-13) ALBERTON. S. G.; MEDINA, N. H.; ADDED, N.; AGUIAR, V. A. P.; Marcilei Aparecida Guazzelli; Roberto Santos© 2021 IEEE.Lackner's theory for avalanche multiplication in semiconductor devices provides physical interpretation for the model parameters and obtaining them through experimental methods is necessary. In this work, the charge collection mechanisms of heavy-ion-induced avalanche multiplication in power MOSFETs are studied based on Lackner's impact ionization model. The heavy-ion-induced impact ionization coefficients were estimated by comparing collected charge values obtained from computational simulations and experimental measurements.
- First successful SEE measurements with heavy ions in Brazil(2014-07-18) MEDINA, N. H.; Marcilei Aparecida Guazzelli; ADDED, N.; AGUIAR. V. A . P.; Renato Giacomini; MACHIONE, E. L. A.; DE MELO, M. A. A.; SANTOS, R. B. B.; SEIXAS, L. E.© 2014 IEEE.In this work, the first successful SEE measurements with heavy ions in Brazil is reported. The heavy ions were produced at the São Paulo 8 UD Pelletron accelerator. 12C, 16O, 19F, 28Si, 35Cl, 63Cu and 107Ag heavy ion beams were used to test a commercial off-the-shelf transistor. During irradiation, the response of a pMOS transistor was continuously monitored to measure the SEE events. In order to achieve a uniform low intensity beam the heavy ions were Rutherford scattered at 15 by a 275 μg/cm2 gold foil.
- Analyzing the influence of the angles of incidence on SEU and MBU events induced by low LET heavy ions in a 28-nm SRAM-based FPGA(2017) TONFAT, J.; KASTENSMIDT, F. L.; ARTOLA, L.; HUBERT, G.; MEDINA, N. H.; ADDED, N.; AGUIAR, V. A. P.; AGUIRRE, F.; MACCHIONE, E. L. A.; Marcilei Aparecida Guazzelli© 2016 IEEE.This work highlights the impact of low LET heavy ions particles on the reliability of 28-nm Bulk SRAM cells from 4rtix-7 FPGA. Radiation tests showed significant differences in he MBU cross section of configuration (CRAM) and BRAM memory cells under various angles of incidence. Radiation results re compared with simulations at transistor level by using the ioft error tool, MUSCA SEP3 (MUlti-SCAle Single Event henomenon Prediction Platform) coupled with circuit imulations with the aim to analyze the differences of upset ensitivity as a function of layout SRAM. This analysis leads to etermine the correct layout and technology used in the tested PGA. By using the detailed classification of MBU events, it is ossible to analyze the effectiveness of correction mechanisms of he FPGA configuration memory.
- Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces with Design Diversity Redundancy(2020-03-05) GONZALEZ, C. J.; ADDED, N.; MACCHIONE, E. L. A.; AGUIAR, V. A. P.; KASTENSMIDT, F. G. L.; PUCHNER, H. K.; Marcilei Aparecida Guazzelli; MEDINA, N. H.; BALEN, T. R.© 1963-2012 IEEE.In this article, a commercial programmable system-on-chip (PSoC 5, from Cypress Semiconductor) is tested under heavy-ion irradiation with a focus on the analog-to-digital interface blocks of the system. For this purpose, a data acquisition system (DAS) was programmed into the device under test and protected with a design diversity redundancy technique. This technique implements different levels of diversity (architectural and temporal) by using two different architectures of converters (a Σ Δ converter and two successive approximation register (SAR) converters) operating with distinct sampling rates. The experiment was performed in a vacuum chamber, using a 16O ion beam with 36-MeV energy and sufficient penetration into the silicon to produce an effective linear energy transfer (LET) of 5.5 MeV/mg/cm2 at the active region. The average flux was approximately 350 particles/s/cm2 for 246 min. The individual susceptibility of each converter to single-event effects is evaluated, as well as the whole system cross section. Results show that the proposed technique is effective to mitigate errors originating at the converters since 100% of such errors were corrected by using the diversity redundancy technique. Results also show that the processing unit of the system is susceptible to hangs that can be mitigated using watchdog techniques.