Departamento de Física

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Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects
(2016) Benfica J.; Green B.; Porcher B.C.; Poehls L.B.; Vargas F.; Medina N.H.; Added N.; De Aguiar V.A.P.; Macchione E.L.A.; Aguirre F.; Silveira M.A.G.; Perez M.; Sofo Haro M.; Sidelnik I.; Blostein J.; Lipovetzky J.; Bezerra E.A.
© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241 AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.