Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion

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dc.contributor.authorRodrigo Doria
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorTREVISOLI, R. D.
dc.contributor.authorMichelly De Souza
dc.contributor.authorLEE, C.-W.
dc.contributor.authorFERAIN, I.
dc.contributor.authorAKHAVAN, N. D.
dc.contributor.authorYAN, R.
dc.contributor.authorRAZAVI, P.
dc.contributor.authorYU, R.
dc.contributor.authorFRANTI, A.
dc.contributor.authorCOLINGE, J-P.
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.date.accessioned2023-08-26T23:49:31Z
dc.date.available2023-08-26T23:49:31Z
dc.date.issued2011-09-05
dc.description.abstractThis paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
dc.description.firstpage114
dc.description.issuenumber2
dc.description.lastpage121
dc.description.volume6
dc.identifier.citationDORIA, R.; PAVANELLO, M. A.; TREVISOLI, R. D.; DE SOUZA, M.; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P. Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion. Journal of Integrated Circuits and Systems, v. 6, n. 2, p. 114-121, sept. 2011.
dc.identifier.issn1807-1953
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4978
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.rightsAcesso Restrito
dc.subject.otherlanguageAnalog operation
dc.subject.otherlanguageHarmonic distortion
dc.subject.otherlanguageJunctionless
dc.subject.otherlanguageMultiple gate transistor
dc.subject.otherlanguageSilicon-on-insulator
dc.titleAnalog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion
dc.typeArtigo
fei.scopus.citations17
fei.scopus.eid2-s2.0-82255162478
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=82255162478&origin=inward
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