Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors

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dc.contributor.authorCONTRERAS, E.
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorALVARADO, J.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2023-08-26T23:49:58Z
dc.date.available2023-08-26T23:49:58Z
dc.date.issued2010-09-05
dc.description.abstractThe development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
dc.description.firstpage110
dc.description.issuenumber2
dc.description.lastpage115
dc.description.volume5
dc.identifier.citationCONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; PAVANELLO, M. A. Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors. Journal of Integrated Circuits and, v. 5, n. 2, p. 110-115, sept. 2010.
dc.identifier.issn1872-0234
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/5006
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.rightsAcesso Restrito
dc.subject.otherlanguage2D ATLAS simulation
dc.subject.otherlanguageDouble-gate graded-channel transistor
dc.subject.otherlanguageSmartspice simulator
dc.subject.otherlanguageSymmetric doped double-gate model
dc.titleApplication of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
dc.typeArtigo
fei.scopus.citations9
fei.scopus.eid2-s2.0-78149240858
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=78149240858&origin=inward
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