Influence of the tunneling gate current on C-V curves

Página do item simplificado
dc.contributor.authorRODRIGUE, M.
dc.contributor.authorSONNENBERG, V.
dc.contributor.authorJoao Antonio Martino
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-8121-6513
dc.date.accessioned2023-08-26T23:50:25Z
dc.date.available2023-08-26T23:50:25Z
dc.date.issued2006-08-28
dc.description.abstractThis paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region. © 2006 The Electrochemical Society.
dc.description.firstpage301
dc.description.issuenumber1
dc.description.lastpage307
dc.description.volume4
dc.identifier.citationRODRIGUE, M.; SONNENBERG, V.; MARTINO, J. A. Influence of the tunneling gate current on C-V curves. ECS Transactions, v. 4, n. 1, p. 301-307, aug. 2006.
dc.identifier.issn1938-6737
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/5035
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleInfluence of the tunneling gate current on C-V curves
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-33847659965
fei.scopus.subjectPolysilicon depletion region
fei.scopus.subjectSubmicrometer CMOS technology
fei.scopus.subjectTunneling gate current
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=33847659965&origin=inward
Arquivos
Coleções
Artigo de evento