Engenharia Elétrica

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Comparison between the behavior of submicron Graded-Channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range
(201-10-14) Michelly De Souza; EMAM, M.; VANHOENACKER-JANVIER, D.; RASKIN, J. P.; FLANDRE, D.; Marcelo Antonio Pavanello
Implementando Algoritmos de Visão Computacional em VHDL
(2002-01-05) SOUZA, PAULO VINÍCIUS DE; Reinaldo Bianchi
Partidas de futebol entre robôs constituem uma atividade que possibilita a realização de experimentos reais para o desenvolvimento e testes de robôs, que apresentam comportamento inteligente e que cooperam entre si para a execução de uma tarefa, formando um time. Este artigo descreve o projeto e a implementação do sistema de visão computacional baseado em hardware reconfigurável tipo FPGA para ser utilizado em um time de robôs. Para tanto, são apresentadas a linguagem de definição de hardware VHDL, a descrição dos algoritmos de visão computacional adotados para tratar os problemas específicos do domínio estudado, bem como o sistema implementado. Finalmente, é realizada uma comparação da eficiência do sistema com implementações em software (linguagem C) dos mesmos algoritmos.
A Methodology to Model And Simulate An Environment For E-Learning
(2003) NEVE, Alessandro La;LA NEVE, ALESSANDRO; BROSSO, Maria Inês
Procesador Reprogramable para Compresión y Descompresión, PRCD en Tiempo Real de Imágenes de Video Digital
(2003-01-05) MELO, MARCO ANTONIO ASSIS DE; NEVE, A. L.
Halo effects on 0.13 μm floating-body partially depleted SOI n-Mosfets in low temperature operation
(2003-10-12) MARTINO, J. A.; Marcelo Antonio Pavanello; SIMOEN, E.; CLAEYS, C.
This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation, Parameters such as the Drain Induced Barrier Lowering and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 - 300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.
Operation of double gate graded-channel transistors at low temperatures
(2003-10-16) Marcelo Antonio Pavanello; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D.
This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.
Wavelets application in electrostatic and their computing aspects.
(2004) Aldo Belardi; CARDOSO, José Roberto; SARTORI, Carlos Antonio França
Heuristically accelerated Q-learning: A new approach to speed up reinforcement learning
(2004-01-05) Reinaldo Bianchi; RIBEIRO, C. H. C.; COSTA, A. H. R.
This work presents a new algorithm, called Heuristically Accelerated Q-Learning (HAQL), that allows the use of heuristics to speed up the well-known Reinforcement Learning algorithm Q-learning. A heuristic function H that influences the choice of the actions characterizes the HAQL algorithm. The heuristic function is strongly associated with the policy: it indicates that an action must be taken instead of another. This work also proposes an automatic method for the extraction of the heuristic function H from the learning process, called Heuristic from Exploration. Finally, experimental results shows that even a very simple heuristic results in a significant enhancement of performance of the reinforcement learning algorithm. © Springer-Verlag 2004.
Wavelet's application in electrostatic and their computing aspects
(2004-01-05) Aldo Belardi; Cardoso J. R.; Sartori C. A. F.
This paper presents the mathematical basis, and some results, concerning the application of the Haar's Wavelets as the expansion function in the method of moments. Some computational optimization techniques are used, and their main aspects are stressed in the paper. As an example, the surface charge density on a finite and thin plane plate calculation is presented, in winch the main computational performance aspects are evaluated.
Stocks classification using fuzzy clustering
(2004-06-21) Renato Aguiar; SALES, R. M.; DE SOUSA, L. A.; IMONIANA, J. O.
The main objective of this paper is to investigate the application of a pattern recognition technique as a supporting tool for stock investment decision taking by the public companies in the Brazilian Stock Market. The technique, known as fuzzy clustering means is applied to a set of indexes extracted from the quarterly financial statements relating to the 4 th quarter of 1994 through the 2nd quarter of 2002 belonging to oil/petrochemical and textile companies. The technique separates a group of companies into two sets. Having a set with higher potential returns than the other. And besides that, the set of stocks of the companies produced a higher potential yields and an average financial returns closer to the Bovespa index.
Digital signal processing with MatLab and DSP Kits
(2004-08-04) MELO, M. A. A. DE; Fabrizio Leonardi; LA NEVE, A.
A methodology, based on progressive steps, has been developed, so that the students be prepared to design and implement typical industrial projects, such as digital filters, voice processing algorithms, and others, and also be able to correlate this knowledge with other disciplines. They start with an analog system, described by a differential equation, from which a generic discrete equation is generated. The projects are initially simulated with MatLab, and they are then implemented with DSP TMS320C31. The projects are always based on a fundamental equation of differences, representing a digital filter: this is very important for the study of digital processing concepts, such as system stability, system order, computational complexity, and so on. The simulation helps the students to understand a system digitalization process. The results obtained with the students in the course show the efficiency of this methodology. ©2004 IEEE.
Distributed DSP processing for multivariable state equations
(2004-08-04) Fabrizio Leonardi; MELO, M. A. A. DE; LA NEVE, A.
This work deals with the synthesis of a multivariable digital controller when its hardware must be decentralized. Thus, it can be used as a way to implement dynamic equations in state space for hardware with limited inputs and outputs. The method consists in breaking equations, while keeping the overall transfer matrix, resulting in a distributed implementation. The solution has a modular structure for an arbitrary number of inputs and outputs. It is shown a way to perform the synthesis by using the same dynamic matrix. As a consequence the computational demand could not be severely reduced when compared with a centralized controller. Nevertheless, the synthesis is actually distributed since each part is implemented with a smaller number of inputs and outputs. A multivariable controller of an inverted pendulum is used as an example. ©2004 IEEE.
Application of Haar's wavelets in the method of moments to solve electrostatic problems
(2004-09-01) Aldo Belardi; ROBERTO CARDOSO J.; FRANCA SARTORI, C. A.
Presents the mathematical basis and some results, concerning the application of Haar's wavelets, as an expansion function, in the method of moments to solve electrostatic problems. Two applications regarding the evaluation of linear and surface charge densities were carried out: the first one on a finite straight wire, and the second one on a thin square plate. Some optimization techniques were used, whose main computational performance aspects are emphasized. Presents comparative results related to the use of Haar's wavelets and the conventional expansion functions. © 2004, Emerald Group Publishing Limited
An improved model for the triangular SOI misalignment test structure
(2004-09-07) Renato Giacomini; MARINO, J. A.
The triangular misalignment test structure is an arrangement of MOS transistors to calculate the poly and source/drain diffusion misalignment as a function of drain current differences. Although these structures have non-rectangular shapes, which may be detrimental for the design, the advantage of measuring currents instead of voltage differences make them very useful. This work presents a new analytic misalignment error model for thin-film, fully depleted SOI technology, using non rectangular devices. Three-dimensional numerical simulation is used as a reference for models comparison and verification. These simulation results show that the proposed analytical model presents an improved performance compared to those available in the literature.
A fully analytical continuous model for graded-channel SOI MOSFET for analog applications
(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.
In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.
Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
Improved current mirror performance using graded-channel silicon-on-insulator devices in high temperature operation
(2004-09-11) FERREIRA, R. S.; Marcelo Antonio Pavanello
This work studies the output characteristics of analog current mirror using graded-channel in comparison to conventional Silicon-On-Insulator MOSFETs in high temperature operation. The output characteristics are discussed, based on simulation and experimental results. The Mirroring Precision, Output Swing and Output Resistance are extremely improved at high temperature thanks to the reduced output conductance in graded-channel transistors.
Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures
(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.
This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.
Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
(2004-09-11) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
The use of partially depleted deep-submicrometer SOI nMOSFETs in mixed mode applications is discussed in terms of channel engineering and temperature of operation. It is shown that the halo implantation used to obtain better digital characteristics degrades the gain and the unity gain frequency in comparison to devices that are not subjected to this implantation.
On-resistance and harmonic distortion in graded-channel SOI FD MOSFET
(2004-11-05) CERDEIRA, A.; ALEMAN, M. A.; Marcelo Antonio Pavanello; MARTINO, J. A.; VANCAILLIE, L.; FLANDRE, D.
In this paper we analyze the advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications, i.e. on-resistance and non-linear harmonic distortion, is supported by measurements on conventional and Graded-Channel (GC) fully depleted (FD) SOI MOSFETs. The quasi linear I-V characteristics of GC transistors demonstrate a decrease of the on-resistance as the length of the low doped region into the channel is augmented and an improvement of the third order harmonic distortion (HD3), when compared with conventional transistors. A full comparison method between conventional and GC SOI MOSFETs is presented considering HD3 evolution with on-resistance tuning under low voltage of operation, demonstrating the significant advantages of the asymmetrical long channel transistors. © 2004 IEEE.

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