Engenharia Elétrica

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https://repositorio.fei.edu.br/handle/FEI/21

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Navegando Engenharia Elétrica por Assunto "A. Semiconductors"

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    Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures
    (2009) de Souza M.; Flandre D.; Pavanello M.A.
    This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. © 2009 Elsevier Ltd. All rights reserved.
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    Cryogenic operation of FinFETs aiming at analog applications
    (2009) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.
    FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. © 2009 Elsevier Ltd. All rights reserved.