Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS(2006) Gimenez S.P.; Pavanello M.A.; Martino J.A.; Flandre D.This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis. © 2005 Elsevier Ltd. All rights reserved.
- Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications(2006) Pavanello M.A.; Der Agopian P.G.; Martino J.A.; Flandre D.We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. © 2005 Elsevier Ltd. All reserved.
- High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures(2005) Pavanello M.A.; Martino J.A.; Raskin J.-P.; Flandre D.This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate SOI transistors at low temperatures from room temperature down to 95 K. Two-dimensional simulations performed here provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs, showing significantly reduced electric field and hence impact ionization rate, which is well known to plague the output characteristics of SOI MOSFETs in the low temperature range. The Early voltage degrades as the temperature decreases but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150-300 K due to compensation provided by the transconductance over drain current ratio. The graded-channel structure can finally improve the intrinsic gain of conventional double gate transistor from 67 dB to 90 dB at 300 K. In the range of L LD/L between 0.20 and 0.35, the gain reaches 90 dB and is weakly temperature-dependent with less than 10% reduction in the range of 300 K down to 95 K. © 2005 Elsevier Ltd. All rights reserved.