Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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18 resultados
Resultados da Pesquisa
- Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware(2023-05-05) KRAUSE, I.; DANTA, L. P.; Salvador Gimenez© 2023, Brazilian Microelectronics Society. All rights reserved.This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. Results show that the EDF algorithm running in IHM-Plasma's hardware has increased the number of tasks executed per second by up to 174% compared to the same algorithm running in software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.
- The Second Generation of Layout Styles to Further Boost the Electrical Performance of Analog MOSFETs(2022-09-17) SILVA, G. A. DA; Salvador Gimenez© 2022, Brazilian Microelectronics Society. All rights reserved.Previous studies have shown that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal), and Ellipsoidal gate shapes for the imple-menting of the planar and three-dimensional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) are capable of boosting their analog and digital electrical per-formances, ionizing radiation tolerances, and reducing the die areas used in comparison to those transistors designed with conventional rectangular layout styles. In order to further boost these features obtained by the use of the first generation of layout styles, one of elements of the second generation of layout styles for MOSFETs, entitled Half-Diamond, is being intro-duced. This new proposal is an evolution of the Diamond layout style, which is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects promoted by the first generation. This layout style can also reduce the effective channel lengths of MOSFETs in comparison to those reached by the Diamond layout style. In this context, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond, and Conventional layout styles, considering they present the same gate areas, bias conditions, and the 180 nm Bulk CMOS ICs technology node. The experimental results show that the satu-ration drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in MOSFETs counterparts, designed with the conventional rectangular gate shape (CMs).
- Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs(2022) GALEMBECK, E. H. S.; Salvador Gimenez; MORETO, R. A. D. L.© 2022 by the authors.The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.
- Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET(2022-08-22) DE LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GALEMBECK, E. H. S.; Salvador Gimenez; CAMILO, L. M.© 2022 IEEE.The zero temperature coefficient (ZTC) is investigated by the simple model and three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectangular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC) technology. A simple model is used to study the behavior of the gate voltage at ZTC (VZTC) in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for EM and CM devices. The VZTC changes in the temperature range investigated showed a temperature mobility degradation dependence and the both devices showed the same behavior. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with 3D simulations results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region.
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.
- Comparative study between conventional and wave planar power mosfets(2021-08-27) SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.One of most challenges of nanoelectronics area is to further increase the integration capacity and electrical performance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs). Several approaches have been done to reach this challenges, as for instance, the use of different fabrication processes, new transistors structures (bi and tridimensional), new materials etc. An alternative strategy, in which it is capable of reducing the total die area, mainly of the analog Complementary MOS (CMOS) integrated circuits (ICs), without affecting their electrical performance, is the use non-standard gate geometries (Diamond, Octo, Ellipsoidal, Fish, Wave etc.) for MOSFETs, instead of the rectangular one commonly used today. Previous studies have shown that by using Wave MOSFETs as a basic cell of the Planar Power MOSFETs (PPM) was able to reduce their total die areas. Therefore, the motivation of this paper is to verify by experimental data, the electrical behavior of PPM implemented with Wave layout style in relation to the one of PPM layouted with the conventional rectangular MOSFETs. The CMOS ICs technology used to manufacture these devices was of 350nm-ON Semiconductor. The main finding of this work is that the Wave MOSFET used as a base cell of a PPM (Wave PPM) present a similar electrical characteristics, but it is responsible to reduce in 9.7% its die area in comparison to the one found in PPM layouted with conventional MOSFETs and therefore, the Wave layout style is an alternative layout to reduce the total die area of PPM. c2021 IEEE.
- The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs(2021-08-27) GALEMBECK, E.H. S.; SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.This article describes, for the first time, the study of electrical behavior of the first element belonging to the family of Second Generation of layout styles for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), entitled Half-Diamond. It was conceived in order to further boosting the electrical performance of the analog MOSFETs in relation to the one found in Diamond MOSFETs (hexagonal gate shape). This innovative layout style has by objective further enhance the Longitudinal Corner Effect (LCE) and mainly the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) by the means of further reducing of the effective channel lengths of Diamond MOSFETs in relation to those measured in the conventional (rectangular gate geometry) ones (RMs). The main results found by the three-dimensional numerical simulations indicates that the Half-Diamond MOSFET (HDM) is able to provide a saturation drain current 13% higher than the one observed in the RM counterpart. Furthermore, the electrical behaviors of LCE, PAMDLE and DEPAMBRE in HDM are analyzed in detail by observing the electrical behavior of the electrostatic potentials, longitudinal electric fields and drain current densities. c2021 IEEE.
- Using the hexagonal layout style for mosfets to boost the device matching in ionizing radiation environments(2020-01-05) PERUZZI, V. V.; CRUZ, W. S.; SILVA, G. A.; SIMOEN, E.; CLAEYS, C.; Salvador Gimenez© 2020, Brazilian Microelectronics Society. All rights reserved.This paper describes an experimental comparative study of the mismatching between the Diamond (hexagonal gate geometry) and Conventional (rectangular gate shape) n-chan-nel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Sili-con-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with an alpha (α) angle equal to 90˚ for MOSFETs is capable of re-ducing the device mismatching by at least 17% regarding the electrical parameters studied as compared to the Conventional MOSFET (CnM) counterparts. Therefore, the Diamond layout style can be considered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs.
- Zero temperature coefficient behavior for ellipsoidal mosfet(2020-01-05) BRAGA DE LIMA, M. P.; CAMILO, L. M.; PEIXOTO, M. A. P.; CORREIA, M. M.; Salvador Gimenez© 2020, Brazilian Microelectronics Society. All rights reserved.The zero temperature coefficient (ZTC) is investi-gated by three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectan-gular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC). In this work an improved simple model which predicts the ZTC point taking into account only the mobility degradation factor (c) and threshold voltage (Vth) parameters as function of temperature is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the mobility degradation factor. Alt-hough simple, the model predictions present a good agreement with the numerical simulations results.