Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
Artigo 0 Citação(ões) na Scopus Boosting the MOSFETs matching by using diamond layout style(2017-04-05) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador Gimenez© 2017, Brazilian Microelectronics Society. All rights reserved.This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.- Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware(2023-05-05) KRAUSE, I.; DANTA, L. P.; Salvador Gimenez© 2023, Brazilian Microelectronics Society. All rights reserved.This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. Results show that the EDF algorithm running in IHM-Plasma's hardware has increased the number of tasks executed per second by up to 174% compared to the same algorithm running in software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.
- The Second Generation of Layout Styles to Further Boost the Electrical Performance of Analog MOSFETs(2022-09-17) SILVA, G. A. DA; Salvador Gimenez© 2022, Brazilian Microelectronics Society. All rights reserved.Previous studies have shown that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal), and Ellipsoidal gate shapes for the imple-menting of the planar and three-dimensional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) are capable of boosting their analog and digital electrical per-formances, ionizing radiation tolerances, and reducing the die areas used in comparison to those transistors designed with conventional rectangular layout styles. In order to further boost these features obtained by the use of the first generation of layout styles, one of elements of the second generation of layout styles for MOSFETs, entitled Half-Diamond, is being intro-duced. This new proposal is an evolution of the Diamond layout style, which is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects promoted by the first generation. This layout style can also reduce the effective channel lengths of MOSFETs in comparison to those reached by the Diamond layout style. In this context, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond, and Conventional layout styles, considering they present the same gate areas, bias conditions, and the 180 nm Bulk CMOS ICs technology node. The experimental results show that the satu-ration drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in MOSFETs counterparts, designed with the conventional rectangular gate shape (CMs).
- Performance of OCTO layout style on SOI MOSFET switches under high-temperature operation(2019-01-05) GALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; Salvador Gimenez© 2019, Brazilian Microelectronics Society. All rights reserved.The present paper performs an experimental comparative study of the main switching electrical parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named Octo SOI MOSFET (OSM), in comparison with the typical rectangular one, regarding a large range of temperature, varying from 300 K to 573 K. The devices were manufactured in a 2 µm fully-depleted SOI (CMOS) technology and are n-type. The results have shown that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE), which are intrinsic effects of the gate octagonal structure of the MOSFET. Besides, it is able to present a higher electrical performance as compared to its rectangular SOI MOSFET (RSM) counterpart (same channel width and bias conditions). As an illustration, the OSM on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller as compared to those found in its RSM counterpart.
- Using the hexagonal layout style for mosfets to boost the device matching in ionizing radiation environments(2020-01-05) PERUZZI, V. V.; CRUZ, W. S.; SILVA, G. A.; SIMOEN, E.; CLAEYS, C.; Salvador Gimenez© 2020, Brazilian Microelectronics Society. All rights reserved.This paper describes an experimental comparative study of the mismatching between the Diamond (hexagonal gate geometry) and Conventional (rectangular gate shape) n-chan-nel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Sili-con-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with an alpha (α) angle equal to 90˚ for MOSFETs is capable of re-ducing the device mismatching by at least 17% regarding the electrical parameters studied as compared to the Conventional MOSFET (CnM) counterparts. Therefore, the Diamond layout style can be considered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs.
- Zero temperature coefficient behavior for ellipsoidal mosfet(2020-01-05) BRAGA DE LIMA, M. P.; CAMILO, L. M.; PEIXOTO, M. A. P.; CORREIA, M. M.; Salvador Gimenez© 2020, Brazilian Microelectronics Society. All rights reserved.The zero temperature coefficient (ZTC) is investi-gated by three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectan-gular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC). In this work an improved simple model which predicts the ZTC point taking into account only the mobility degradation factor (c) and threshold voltage (Vth) parameters as function of temperature is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the mobility degradation factor. Alt-hough simple, the model predictions present a good agreement with the numerical simulations results.