Performance of OCTO layout style on SOI MOSFET switches under high-temperature operation

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2019-01-05
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GALEMBECK, E. H. S.
FLANDRE, D.
RENAUX, C.
Salvador Gimenez
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Journal of Integrated Circuits and Systems
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GALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; GIMENEZ, S. Performance of OCTO layout style on SOI MOSFET switches under high-temperature operation. Journal of Integrated Circuits and Systems,v. 14, n. 1, p. 1-8, Jan, 2019.
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© 2019, Brazilian Microelectronics Society. All rights reserved.The present paper performs an experimental comparative study of the main switching electrical parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named Octo SOI MOSFET (OSM), in comparison with the typical rectangular one, regarding a large range of temperature, varying from 300 K to 573 K. The devices were manufactured in a 2 µm fully-depleted SOI (CMOS) technology and are n-type. The results have shown that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE), which are intrinsic effects of the gate octagonal structure of the MOSFET. Besides, it is able to present a higher electrical performance as compared to its rectangular SOI MOSFET (RSM) counterpart (same channel width and bias conditions). As an illustration, the OSM on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller as compared to those found in its RSM counterpart.

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