Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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20121

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Periódico: search.filters.ispartof.2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012Assunto: search.filters.subject.MOSFETs

Resultados da Pesquisa

Agora exibindo 1 - 2 de 2
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    Artigo de evento 5 Citação(ões) na Scopus
    AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
    (2012) DE LIMA, MORETO R. A.; THOMAZ, C. E.; Salvador Gimenez
    Analog integrated circuits (ICs) design is a complex task due to the large number of input variables that must be determined simultaneously in order to achieve different multiple design goals of an analog integrated circuit design, such as voltage gain (A V), unit voltage gain frequency (f T), slew-rate (SR), harmonic distortion (THD), etc. By using an evolutionary system based on Genetic Algorithm (AG) integrated to the SPICE simulator, named AGSPICE, this work aims to study, understand and calculate the different correlations between the MOSFETs inversion regimes and the design goals of an operational transconductance amplifier (OTA) operating in different design features. We believe that the AGSPICE can provide new design recommendations for the designers and reduce the design cycle time as well. Our experimental results with the AGSPICE are also compared to the results obtained manually and present compatible solutions to other works available in the related literature. © 2012 IEEE.
  • N/D
    Artigo de evento 13 Citação(ões) na Scopus
    Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
    (2012-03/17) MARINIELLO, G.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello; TREVISOLI, R. D. G.
    Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.