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Engenharia Elétrica

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20171

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Periódico: search.filters.ispartof.2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016Assunto: search.filters.subject.Analog behavior

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    Artigo de evento 2 Citação(ões) na Scopus
    Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors
    (2017-10-10) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.
    This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.