Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors
N/D
Tipo de produção
Artigo de evento
Data de publicação
2017-10-10
Texto completo (DOI)
Periódico
2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
Editor
Texto completo na Scopus
Citações na Scopus
2
Autores
Rodrido Doria
TREVISOLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
FLANDRE, D.
Orientadores
Resumo
This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.
Citação
DORIA, T.; DE SOUZA, M.; PAVANELLO, M. A.; FLANDRÉ, D. Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors. 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016. oCT. 2016.
Palavras-chave
Keywords
Active Substrate Bias; Analog Behavior; Self-Cascode Structure; UTBB SOI
Assuntos Scopus
Active substrates; Analog behavior; Analog performance; Back-gate bias; Current mirrors; Equivalent channels; Self-cascode; UTBB SOI