Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
2 resultados
Resultados da Pesquisa
- Asymmetric self-cascode current-voltage constructing algorithm for analog figures-of-merit extraction(2018-08-31) D' OLIVEIRA, L. M.; Michelly De Souza; KILCHYTSKA, V.; FLANDRE. D.© 2018 IEEE.This paper proposes an analysis of a self-cascode IV constructing algorithm for the extraction of DC analog figures of merit, namely the transconductance, output conductance and intrinsic voltage gain. The algorithm was applied on input tables of measured single Fully-depleted Silicon on Insulator (FDSOI) nMOSFETs and was validated on the measured self-cascode association of these devices. The results show an appropriate accuracy, that reflect trends and values with low error.
- Analysis of the output conductance degradation with the substrate bias in SOI UTB and UTBB transistors(2018-08-31) FERNO COSTA, J.; TREVISOLI, R.; Rodrigo Doria© 2018 IEEE.The goal of this work is to present the behavior of the output conductance in Ultra-Thin Body (UTB) and Ultra-Thin Body and Buried Oxide (UTBB) SOI {MOSFETs with the application of a selected set of back gate biases (VSUB) through AC simulations, in devices with and without considering the effect of the ground plane. It has been shown that the output conductance degradation due to self-heating and substrate effects increases as the substrate bias is reduced. The output conductance degradation by self-heating presents a reduction of about 52% and by substrate effects of 57% by simply increasing the back bias from-2V up to 2 V.