Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.
- A New Method for Series Resistance Extraction of Nanometer MOSFETs(2017-07-05) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; BARRAUD, S.; VINET, M.; CASSE, M.; REIMBOLD, G.; FAYNOT, O.; GHIBAUDO, G.; Marcelo Antonio PavanelloThis paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic curve. The method is based on the Y-function curve, such that the series resistance is obtained through the curve of the total resistance as a function of the inverse of the Y-function. It includes both first-and second-order mobility degradation factors. To validate the proposed method, numerical simulations have been performed for devices of different characteristics. Besides, the method applicability has been demonstrated for experimental silicon nanowires and FinFETs. Apart from that, devices with different channel lengths can be used to estimate the mobility degradation factor influence.
- Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors(2020-24-24) TREVISOLI, RENAN; Marcelo Antonio Pavanello; CAPOVILLA, CARLOS EDUARDO; BARRAUD, SYLVAIN; DORIA, RODRIGO TREVISOLIThis article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model's applicability and accuracy.