Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
Artigo 1 Citação(ões) na Scopus Origin of the low-frequency noise in the asymmetric self-cascode structure composed by fully depleted SOI nMOSFETs(2017-08-05) ASSALTI, R.; Rodrigo Doria; FLANDRE, D.; Michelly De Souza© 2017, Brazilian Microelectronics Society. All rights reserved.In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.- Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs(2018) Assalti R.; Flandre D.; de Souza M.© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.