Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- Estimating temperature dependence of generation lifetime extracted from drain current transients(2006-05-01) MARTINO, J. A.; Milene Galeti; RAFI, J. M.; MERCHA, A.; SIMOEN, E.; CLAEYS, C.This paper presents an analysis of the temperature influence on the generation lifetime determination using drain-current transients in floating body partially depleted silicon-insulator n-type metal-oxide-semiconductor field effect transistors fabricated in a 0.13-μm SOI complementary metal-oxide semiconductor technology. The device parameters used to calculate the generation lifetime are studied as a function of the temperature from 20 to 80°C. A sensitivity analysis is done as a function of the gate oxide thickness and silicon film concentration, and the influence on the generation lifetime determination is studied. A simple model to estimate the generation lifetime is proposed. The model is experimentally applied and a good agreement is obtained. All the work is supported by two-dimensional numerical simulation. © 2006 The Electrochemical Society. All rights reserved.
- Uniaxial and/or biaxial strain influence on MuGFET devices(2012-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the impact of global andor local strain engineering techniques on tri-gate p- and nMuGFETs performance is experimentally evaluated. Multiple gate structures were analyzed through basic and analog performance parameters for four different splits processed with different strain-engineering techniques (unstrained, uniaxial, biaxial and uniaxial+biaxial stress). While n-channel devices with narrow fins present a worse analog behavior, biaxial stress promotes the electron mobility for larger devices increasing the voltage gain. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. Although pMuGFETs are less affected by the strain engineering, they present better analog behavior for all studied devices. © 2012 The Electrochemical Society.
- FISH SOI MOSFET: Modeling, characterization and its application to improve the performance of analog ICs(2011) Gimenez S.P.; Alati D.M.; Simoen E.; Claeys C.This paper is conceptual and introduces a new transistor layout style called FISH SOI MOSFET (FSM). It is an evolution of the Diamond device (DSM) and specially designed to preserve the Longitudinal Corner Effect (LCE) to increase the resultant longitudinal electric field along the channel, that results in an improvement in the average carrier drift velocity in the channel. It presents a gate geometric shape similar to a n"smaller than" (<) mathematical symbol. Unlike the DSM, the FISH layout style brings an innovative possibility in the "lengthening of its effective channel length, defined as Lengthening of Effective Channel Length Effect (LECLE)", keeping the channel length with the minimum dimension allowed by the SOI CMOS process technology used in manufacturing digital ICs applications. It can reduce the die area of digital ICs by using the LECLE of the FISH layout structure style by combining conventional SOI pMOSFETs and FISH nMOSFETs. Thanks to the FSM LECLE, one also can reduce the die area of the current mirrors of analog integrated circuits. For the first time, it is shown that LECLE in the FSM structure is able to increase the Early voltage and consequently to improve significantly the voltage gain of analog ICs. © 2011 The Electrochemical Society.
- Modeling silicon on insulator MOS transistors with nonrectangular-gate layouts(2006) Giacomini R.; Martino J.A.This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results. © 2006 The Electrochemical Society. All rights reserved.
- Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects(2008) Giacomini R.; Martino J.A.Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The corner effects also depend on the inclination angle and doping level. © 2008 The Electrochemical Society.
Artigo ESTIMATING TEMPERATURE DEPENDENCE OF GENERATION LIFETIME EXTRACTED FROM DRAIN CURRENT TRANSIENTS(2006) MARTINO, J. A.; GALETI, M.;Galeti, M;GALETI, MILENE; RAFI, J. M.; MERCHA, A.; SIMOEN, E.; CLAEYS, C.