Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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8 resultados
Resultados da Pesquisa
Artigo de evento 0 Citação(ões) na Scopus Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.Artigo de evento 2 Citação(ões) na Scopus A fully analytical continuous model for graded-channel SOI MOSFET for analog applications(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.- On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks(2021-01-05) Michelly De Souza; DORIA, R.T.; TREVISOLI, R.; BARRAUD, S.; Marcelo Antonio PavanelloIn this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier.
- On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration(2016) De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A.© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.
- Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer(2008) de Souza M.; Flandre D.; Pavanello M.A.In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using GC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with a standard SOI MOSFET, without gain loss or linearity degradation. © 2008 Elsevier Ltd. All rights reserved.
- Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS(2006) Gimenez S.P.; Pavanello M.A.; Martino J.A.; Flandre D.This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis. © 2005 Elsevier Ltd. All rights reserved.
- Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications(2006) Pavanello M.A.; Der Agopian P.G.; Martino J.A.; Flandre D.We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. © 2005 Elsevier Ltd. All reserved.
- High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures(2005) Pavanello M.A.; Martino J.A.; Raskin J.-P.; Flandre D.This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate SOI transistors at low temperatures from room temperature down to 95 K. Two-dimensional simulations performed here provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs, showing significantly reduced electric field and hence impact ionization rate, which is well known to plague the output characteristics of SOI MOSFETs in the low temperature range. The Early voltage degrades as the temperature decreases but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150-300 K due to compensation provided by the transconductance over drain current ratio. The graded-channel structure can finally improve the intrinsic gain of conventional double gate transistor from 67 dB to 90 dB at 300 K. In the range of L LD/L between 0.20 and 0.35, the gain reaches 90 dB and is weakly temperature-dependent with less than 10% reduction in the range of 300 K down to 95 K. © 2005 Elsevier Ltd. All rights reserved.