Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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2 resultados
Resultados da Pesquisa
- Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces with Design Diversity Redundancy(2020-03-05) GONZALEZ, C. J.; ADDED, N.; MACCHIONE, E. L. A.; AGUIAR, V. A. P.; KASTENSMIDT, F. G. L.; PUCHNER, H. K.; Marcilei Aparecida Guazzelli; MEDINA, N. H.; BALEN, T. R.© 1963-2012 IEEE.In this article, a commercial programmable system-on-chip (PSoC 5, from Cypress Semiconductor) is tested under heavy-ion irradiation with a focus on the analog-to-digital interface blocks of the system. For this purpose, a data acquisition system (DAS) was programmed into the device under test and protected with a design diversity redundancy technique. This technique implements different levels of diversity (architectural and temporal) by using two different architectures of converters (a Σ Δ converter and two successive approximation register (SAR) converters) operating with distinct sampling rates. The experiment was performed in a vacuum chamber, using a 16O ion beam with 36-MeV energy and sufficient penetration into the silicon to produce an effective linear energy transfer (LET) of 5.5 MeV/mg/cm2 at the active region. The average flux was approximately 350 particles/s/cm2 for 246 min. The individual susceptibility of each converter to single-event effects is evaluated, as well as the whole system cross section. Results show that the proposed technique is effective to mitigate errors originating at the converters since 100% of such errors were corrected by using the diversity redundancy technique. Results also show that the processing unit of the system is susceptible to hangs that can be mitigated using watchdog techniques.
- Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA under Radiation Effects(2020-07-05) OLIVEIRA, A. B.; TAMBARA, L. A.; BENEVENUTI, F.; BENITES, L. A. C.; ADDED, N.; AGUIAR, V. A. P.; MEDINA, N. H.; Marcilei Aparecida Guazzelli; KASTENSMIDT, F. L.© 1963-2012 IEEE.This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mitigation techniques based on hardware redundancy and scrubbing. Results demonstrated an improvement of $3\times $ in the cross section when scrubbing and coarse grain triple modular redundancy are used. The Rocket processor presented analogous sensitivity to radiation effects as the state-of-the-art soft processors. Due to the complexity of the system-on-chip, not only the Rocket core but also its peripherals should be protected with proper solutions. Such solutions should address the specific vulnerabilities of each component to improve the overall system reliability while maintaining the trade-off with performance.