Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Departamento de Física

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785

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Resultados da Pesquisa

Agora exibindo 1 - 3 de 3
  • Artigo de evento 3 Citação(ões) na Scopus
    X-ray-induced upsets in a Xilinx spartan 3E FPGA
    (2015-12-24) Marcilei Aparecida Guazzelli; Roberto Santos; LEITE, F. G. H.; ARAÚJO, N. E.; MEDINA, N. H.; PORCHER, B. C.; AGUIAR, V. A P.; ADDED, N.; VARGAS. F.
    © 2015 IEEE.As the use of Field Programmable Gate Arrays (FPGAs) in space and in other strategic areas increases, concerns about their tolerance to radiation also increases. This work reports the observation of soft and hard errors in a Xilinx Spartan-3E commercial off-The-shelf FPGA when exposed to low-dose rate, low energy X-rays during a dynamic test in which a LEON 3 soft-core processor was mapped in the FPGA.
  • Artigo de evento 9 Citação(ões) na Scopus
    Analyzing the influence of the angles of incidence on SEU and MBU events induced by low LET heavy ions in a 28-nm SRAM-based FPGA
    (2017) TONFAT, J.; KASTENSMIDT, F. L.; ARTOLA, L.; HUBERT, G.; MEDINA, N. H.; ADDED, N.; AGUIAR, V. A. P.; AGUIRRE, F.; MACCHIONE, E. L. A.; Marcilei Aparecida Guazzelli
    © 2016 IEEE.This work highlights the impact of low LET heavy ions particles on the reliability of 28-nm Bulk SRAM cells from 4rtix-7 FPGA. Radiation tests showed significant differences in he MBU cross section of configuration (CRAM) and BRAM memory cells under various angles of incidence. Radiation results re compared with simulations at transistor level by using the ioft error tool, MUSCA SEP3 (MUlti-SCAle Single Event henomenon Prediction Platform) coupled with circuit imulations with the aim to analyze the differences of upset ensitivity as a function of layout SRAM. This analysis leads to etermine the correct layout and technology used in the tested PGA. By using the detailed classification of MBU events, it is ossible to analyze the effectiveness of correction mechanisms of he FPGA configuration memory.
  • Artigo 6 Citação(ões) na Scopus
    Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces with Design Diversity Redundancy
    (2020-03-05) GONZALEZ, C. J.; ADDED, N.; MACCHIONE, E. L. A.; AGUIAR, V. A. P.; KASTENSMIDT, F. G. L.; PUCHNER, H. K.; Marcilei Aparecida Guazzelli; MEDINA, N. H.; BALEN, T. R.
    © 1963-2012 IEEE.In this article, a commercial programmable system-on-chip (PSoC 5, from Cypress Semiconductor) is tested under heavy-ion irradiation with a focus on the analog-to-digital interface blocks of the system. For this purpose, a data acquisition system (DAS) was programmed into the device under test and protected with a design diversity redundancy technique. This technique implements different levels of diversity (architectural and temporal) by using two different architectures of converters (a Σ Δ converter and two successive approximation register (SAR) converters) operating with distinct sampling rates. The experiment was performed in a vacuum chamber, using a 16O ion beam with 36-MeV energy and sufficient penetration into the silicon to produce an effective linear energy transfer (LET) of 5.5 MeV/mg/cm2 at the active region. The average flux was approximately 350 particles/s/cm2 for 246 min. The individual susceptibility of each converter to single-event effects is evaluated, as well as the whole system cross section. Results show that the proposed technique is effective to mitigate errors originating at the converters since 100% of such errors were corrected by using the diversity redundancy technique. Results also show that the processing unit of the system is susceptible to hangs that can be mitigated using watchdog techniques.