Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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3 resultados
Resultados da Pesquisa
- Dynamic heavy ions SEE testing of NanoXplore radiation hardened SRAM-based FPGA: Reliability-performance analysis(2019) OLIVEIRA, A.; BENEVENUTI, F.; BENITES, L.; RODRIGUES, G.; KASTENSMIDT, F.; ADDED, N.; AGUIAR, V.; MEDINA, N.; Marcilei Aparecida Guazzelli; TAMBARA, L.© 2019 Elsevier LtdNanoXplore is the European pioneer vendor to develop ITAR-free radiation-hardened SRAM-based FPGAs. This work is the first to explore dynamic SEE tests in the NG-Medium FPGA device. The reliability-performance analysis of an embedded unmitigated design is performed under heavy ion-induced errors. Moreover, the improvements of additional user level fault-tolerance techniques, such as redundancy and scrubbing, are explored. The design sensitiveness is evaluated through dynamic cross section, mean fluence to failure, and empiric reliability. Results obtained demonstrate the best tradeoff between area, performance, and reliability is achieved combining full design redundancy, periodic scrubbing, arithmetic functions implemented in DSPs, logical resets between executions, and area-oriented application execution.
- Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA under Radiation Effects(2020-07-05) OLIVEIRA, A. B.; TAMBARA, L. A.; BENEVENUTI, F.; BENITES, L. A. C.; ADDED, N.; AGUIAR, V. A. P.; MEDINA, N. H.; Marcilei Aparecida Guazzelli; KASTENSMIDT, F. L.© 1963-2012 IEEE.This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mitigation techniques based on hardware redundancy and scrubbing. Results demonstrated an improvement of $3\times $ in the cross section when scrubbing and coarse grain triple modular redundancy are used. The Rocket processor presented analogous sensitivity to radiation effects as the state-of-the-art soft processors. Due to the complexity of the system-on-chip, not only the Rocket core but also its peripherals should be protected with proper solutions. Such solutions should address the specific vulnerabilities of each component to improve the overall system reliability while maintaining the trade-off with performance.
- Robust convolutional neural networks in sram-based fpgas: A case study in image classification(2021-08-23) BENEVENUTI, F.; KASTENSMIDT, F.; OLIVEIRA, A.; ADDED, N.; AGUIAR, V.; MEDINA, N.; Marcilei Aparecida Guazzelli© 2021, Brazilian Microelectronics Society. All rights reserved.— This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.