Departamento de Física

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Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID
(2016-05-17) BENFICA, J.; GREEN, B.; PORCHER, B. C.; POEHLS, L. B.; VARGAS, F.; MEDINA, N. H.; ADDED, N.; AGUIAR, V. A. P. DE; MACCHIONE, E. L. A.; AGUIRRE, F.; Marcilei Aparecida Guazzelli
© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.