Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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3 resultados
Resultados da Pesquisa
- Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA under Radiation Effects(2020-07-05) OLIVEIRA, A. B.; TAMBARA, L. A.; BENEVENUTI, F.; BENITES, L. A. C.; ADDED, N.; AGUIAR, V. A. P.; MEDINA, N. H.; Marcilei Aparecida Guazzelli; KASTENSMIDT, F. L.© 1963-2012 IEEE.This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mitigation techniques based on hardware redundancy and scrubbing. Results demonstrated an improvement of $3\times $ in the cross section when scrubbing and coarse grain triple modular redundancy are used. The Rocket processor presented analogous sensitivity to radiation effects as the state-of-the-art soft processors. Due to the complexity of the system-on-chip, not only the Rocket core but also its peripherals should be protected with proper solutions. Such solutions should address the specific vulnerabilities of each component to improve the overall system reliability while maintaining the trade-off with performance.
- Reliability calculation with respect to functional failures induced by radiation in TMR arm cortex-M0 soft-core embedded into SRAM-based FPGA(2019) Benites L.A.C.; Benevenuti F.; De Oliveira A.B.; Kastensmidt F.L.; Added N.; Aguiar V.A.P.; Medina N.H.; Guazzelli M.A.© 2019 IEEE.This paper presents comparative results from fault injection (FI) and heavy ions accelerated irradiation on a Xilinx 7 series static RAM (SRAM)-based field-programmable gate array (FPGA) for a soft-core microprocessor mitigated by triple modular redundancy (TMR) with different levels of granularity. The Arm Cortex-M0 soft-core processor executing two software applications is employed as a case study. The TMR implementation is automatically generated from synthesized netlist and includes coarse and fine grain variants. Apart from the TMR mitigation, the configuration memory scrubbing is used as implemented by the engine natively available on Xilinx 7 series FPGAs. Experiments with FI and heavy ions allow analyzing the effectiveness of the automated TMR mitigation combined with memory scrubbing and also to analyze the consistency of reliability metrics from FI and heavy ions. The dynamic cross section of the design was improved up to 4.5 times according to the implemented TMR granularity and when associated with the configuration memory scrubbing.
- Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs(2018) Tambara L.A.; Kastensmidt F.L.; Rech P.; Lins F.; Medina N.H.; Added N.; Aguiar V.A.P.; Silveira M.A.G.© 1963-2012 IEEE.All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system's susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.