Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

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dc.contributor.authorRIBEIRO, T. A.
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorESTRADA, M.
dc.contributor.authorBARRAUD, S.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-05-01T06:03:02Z
dc.date.available2022-05-01T06:03:02Z
dc.date.issued2022-01-05
dc.description.abstractThis work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical characteristics. By adopting multiple combinations between the fin height (HFIN) and the fin width (WFIN), chosen from the range of published data in the literature, the devices will operate from double-gate (FinFET like) mode towards to nanowire mode. Additionally, junctionless transistors with and without additional doping at the drain and source extensions were studied. Experimentally calibrated 3D TCAD simulations are used to allow for the study of these several combinations. Results show that for long-channel devices the best performance is obtained for tall and narrow fins, leading to the highest on-to-off current ratio (ION/IOFF) and the smallest values of subthreshold swing and DIBL. On the other hand, for short channel devices, independently of the doping level of the extensions, the best results are found for short HFIN and narrow WFIN, leading to the smaller values of subthreshold swing and DIBL, with a high ION/IOFF ratio. However, the use of doped extensions degrades the overall device performance of short-channel junctionless devices as will be demonstrated.
dc.identifier.citationRIBEIRO, T. A.; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.;PAVANELLO, M. A. Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors. Journal of Computational Electronics, 2022.
dc.identifier.doi10.1007/s10825-022-01874-0
dc.identifier.issn1572-8137
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4483
dc.relation.ispartofJournal of Computational Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguage3D TCAD simulation
dc.subject.otherlanguageDouble-gate
dc.subject.otherlanguageElectrical measurements
dc.subject.otherlanguageElectrical parameters
dc.subject.otherlanguageJunctionless
dc.subject.otherlanguageNanowire
dc.subject.otherlanguageTriple-gate
dc.titlePragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors
dc.typeArtigo
fei.scopus.citations2
fei.scopus.eid2-s2.0-85127544159
fei.scopus.subject3d TCAD simulation
fei.scopus.subjectDouble-gate
fei.scopus.subjectElectrical measurement
fei.scopus.subjectElectrical parameter
fei.scopus.subjectFin height
fei.scopus.subjectFin widths
fei.scopus.subjectJunctionless
fei.scopus.subjectPerformance
fei.scopus.subjectTCAD simulation
fei.scopus.subjectTriple-gate
fei.scopus.updated2024-11-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85127544159&origin=inward
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