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Artigo de evento Automatic detection of people with reduced mobility using YOLOv5 and data reduction strategy(2023-05-29) ADORNO, P. L. V.; JASENOVSKI, I. M.; SANTIAGO, D. F. DE M.; Leila Bergamasco© 2023 Copyright held by the owner/author(s).Context: A portion of the users in the São Paulo Metro are people who have physical limitations and need the help of wheelchairs or other similar devices. In this way, the Metro stations have elevators that allow these users to move between the floors of the station. In order, for the elevator to be used, it is necessary for the user to call the operators of the stations, who, in turn, check if the user who is requesting access to the elevator fits the target audience. Problem: This type of request requires manual validation by station operators, causing interruptions in their work routines and delays in passenger travel. Solution: To implement and evaluate artificial intelligence methods for automatic detection of people in wheelchairs or other auxiliary devices. IS Theory: This project was idealized from the perspective of Customer Focus Theory. Method: The You Only Look Once (YOLOv5) neural network was implemented in the Mobility Aids database. Tests were performed considering the original and modified base, composed of a reduced number of images, aiming to assess whether the accuracy of the model remains even with reduced database data. Summary of Results: The results obtained show an average accuracy of more than 92% with the modified database. Contribution: The results corroborated our methodology and we will be able to test in Sao Paulo subway with real images. In a long term, It is expected that by automating such a task, operators will be less overloaded and passengers with reduced mobility will gain more autonomy.Artigo Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.Artigo Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.Artigo Heuristically accelerated Q-learning: A new approach to speed up reinforcement learning(2004-01-05) Reinaldo Bianchi; RIBEIRO, C. H. C.; COSTA, A. H. R.This work presents a new algorithm, called Heuristically Accelerated Q-Learning (HAQL), that allows the use of heuristics to speed up the well-known Reinforcement Learning algorithm Q-learning. A heuristic function H that influences the choice of the actions characterizes the HAQL algorithm. The heuristic function is strongly associated with the policy: it indicates that an action must be taken instead of another. This work also proposes an automatic method for the extraction of the heuristic function H from the learning process, called Heuristic from Exploration. Finally, experimental results shows that even a very simple heuristic results in a significant enhancement of performance of the reinforcement learning algorithm. © Springer-Verlag 2004.Artigo de evento Elbow flexion and extension movements characterization by means of EMG(2008-01-05) BITTAR, L. M.; Castro, M.C.F.Electromyographic (EMG) signal is the electrical manifestation of neuromuscular activation associated with muscle contraction. The present work intends to characterize the behavior of the muscles biceps and triceps during elbow flexion and extension movements, without load. These movements were performed at horizontal and vertical planes. Three types of test were performed, for each plane, relating EMG signal with joint position. Five men volunteers, ages ranged between 18 and 21 years old, were selected to participate to the tests. The first test consisted to move 10 degrees for each three seconds until the allowed maximum flexion and then, to return at the same way to the initial position. For the second test, the same movement was made but continuously, without stopping at intermediate positions. And for the third test, continuously flexion and extension movements were repeated sequentially but for different amplitudes, increasing by 10 degrees each. The tests were repeated, three times each. Initially, graphical analysis of the data was made for standard behavior detection and, for a quantitative analysis, after EMG preprocessing, averages and variation coefficients were calculated from specific intervals at the beginning, middle and at the end of movement. Although an EMG signals inherent variability, results showed inter and intra subject's repeatability, but only for movements performed at the horizontal plane.Artigo de evento Study of circular gate SOI nMOSFET devices at high temperatures(2008-05-12) ALMEIDA, L. M.; BELLODI, M.The aim of this work is to evaluate the drain leakage current behavior in a Circular Gate (CG) SOI nMOSFET fabricated in 0.13 μm SOI CMOS technology. This technology is analyzed operating since room temperature up to 300°C, where the channel length and the geometrical drain bias terminal influence are analyzed in the drain leakage current behavior, when the devices are operating at high temperatures, through 3D numerical simulations. Since the CG SOI nMOSFET is not a symmetrical structure, it is possible to have two different configurations as following: the one which structure is configured with external drain and another one, with internal drain. Analyzing the drain leakage current behavior as a function of channel length at high temperatures, it is possible to observe that for the same channel length, as the temperature increases, it becomes higher and it increases as the channel length reduces. On the other hand, when the devices are operating with external drain, the drain leakage current becomes lower as compared to the internal drain, for both devices operating at same conditions. The results show that the drain leakage current depends strongly on the channel length and its density distribution is non uniform along the silicon film thickness. Besides it, also was observed that the drain leakage current depends on drain terminal configuration. Then, in order to understand the drain configuration influence in the drain leakage current behavior at high temperatures, the electric field was analyzed into the silicon film.Artigo Study of matching properties of graded-channel SOI MOSFETs(2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.Artigo The Haar wavelets used how expansion function in the method of the moments in the solution of some electrostatic problems(2010-08-05) Aldo Belardi; CARDOSO, J. R.; SARTORI, C. A. F.This work presents the methodology from the determination the charge superficial density and electrical fields, in three simple structures to a finite straight wire, square plane plates and the capacitance between to plane plate, all finite and submitted to a constant potential. That involves the method of the moments using as expansion function the Haar wavelets instead of the pulse function, in order to reach a good precision and reducing the computational execution time. We also intend to take advantages of the wavelets application through the Cholesky decomposition, talking about formation of scattered matrixes, and the detection of nulls values.Artigo Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime(2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.Artigo Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs(2010-09-05) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.Artigo Extraction of mobility degradation and source-and-drain resistance in MOSFETs(2010-09-05) MUCI, J.; LATORRE REY, A. D.; GARCIA+SANCHEZ, F. J.; LUGO MUNOZ, D. C.; ORTIZ-CONDE, A.; HO, C. -S.; LIOU, J. J.; Marcelo Antonio Pavanello; Rodrigo DoriaA MOSFET model parameters extraction procedure that overcomes the difficulties of separating the effects of source-and-drain series resistance and mobility degradation factor is presented. Instead of the conventional direct fitting, the present procedure involves the use of indirect bidimensional fitting of the source-to-drain resistance of a single device, as obtained from the below-saturation output characteristics measured at several above-threshold gate voltages. The procedure is verified with a simulated long channel FinFET device with externally added resistances and is later applied to experimental planar bulk DRAM MOSFET devices with channel lengths ranging from 0.23μm to 2.0μm. The procedure is shown to be advantageous in terms of computational efficiency and it is appropriate even with high values of externally added series resistances. For the case of devices with various channel lengths, the accuracy of the procedure is improved if the value of RSD is extracted from the shortest channel length. This value of RSD could be used for extracting the other parameters for devices with longer channel.Artigo Temperature and silicon film thickness influence on the operation of lateral SOI PIN photodiodes for detection of short wavelengths(2011-09-05) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio PavanelloThis work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.Artigo Influence of fin shape and temperature on conventional and strained MuGFETs' analog parameters(2011-09-05) BUHLER, R. T.; Giacomini R.; MARTINO, J. A.This work evaluates two important technological variations of Triple-Gate FETs: the use of strained silicon and the occurrence of non-rectangular body cross-section. The anaysis is focused on the electrical parameters for analog applications, and covers a temperature range from 150 K to 400 K. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes showed that the fin shape can have a major role in some analog parameters than the use of the strained silicon technology, helping to improve those parameters under certain circumstances. The highest intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom at low temperature. Besides the intrinsic voltage gain, were also studied: the threshold voltage, subthreshold swing, drain induced barrier lowering, channel resistance, total harmonic distortion, transconductance, transconductance to drain current ratio, output conductance, Early voltage, drain voltage saturation and unity gain frequency.Artigo QFT control applied to a Drive by Wire (DBW) system(2012-01-05) Delatore F.; Fabrizio Leonardi; CARVALHO, A. T.; MORIOKA, C. A.Tradionally, the throttle valve positioning was performed mechanically by means of a steel cable. Nowadays at the embedded system stage, an electromechanical system named as Drive by Wire (DBW) substitutes the direct positioning. The DBW is controlled by the vehicle Engine Control Unit (ECU) and is responsible to adjust the mass air flow delivered to the engine and to control the idle engine rotation. The throttle valve control is somehow a challenging task because of nonlinear phenomena caused by the spring and the gearbox. The present work aims to design a robust parametric control for a DBW system, using a plant model identified numerically at different operations points. The results show that the controller is able to deal with the nonlinear phenomena providing a reasonable performance with no steady state error and a consistent setting time.Artigo Robust model matching control applied to a crane(2012-01-05) DE CAMPOS, E. L. L.; Fabrizio LeonardiThis paper discusses the robust closed loop control design subject to parametric uncertainties applied to a crane during a maneuver. Usually crane trajectories are generated by formulating a minimum time optimal control in open loop. However, the optimality of the solution is not maintained due to variations in the plant over time. This work proposes the use of a model matching structure to reduce the problems related to model uncertainties thus trying to preserve the trajectory optimality. The robust compensator minimizes explicitly the matching error between the real plant and the reference plant. In this application the main uncertain parameter is the pendulum length and plays the role of the load lifting. To illustrate the application experiments were done using a lab scale equipment. The results observed are very close to those obtained from numerical simulation.Artigo A simple electron mobility model considering the silicon-dielectric interface orientation for circular surrounding-gate transistor(2012-01-05) PERIN, A. L.; PEREIRA, A. S. N.; AGOPIAN, P. G. D.; Joao Antonio Martino; Giacomini R.AIn this work, a simple model that accounts for the variation of electron mobility as a function of the silicondielectric interface crystallographic orientation is presented. Simulations were conducted in order to compute the effective mobility of planar devices and its results were compared to experimental data for several interface orientations. The error between experimental data and the proposed model remained bellow 4%. The model has been applied to nMOS circular surrounding gate (thin-pillar transistor - CYNTHIA) and allowed the observationof current density variations as a function of the interface orientation around the silicon pillar.Artigo Fin cross-section shape influence on short channel effects of mugfets(2012-05-05) BUHLER, R. T.; Giacomini R.; Marcelo Antonio Pavanello; Joao Antonio MartinoMultiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.Artigo Impact of the series resistance in the I-V characteristics of junctionless nanowire transistors and its dependence on the temperature(2012-01-05) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.Artigo Modeling of thin-film lateral SOI PIN diodes with an alternative multi-branch explicit current model(2012-01-05) LUGO-MUNOZ; MUCI, J.; ORTIZ-CONDE, A.; GARCIA-SANCHEZ, F. J.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloWe propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 K. This alternative multi-exponential model can be used for semiconductor junctions which exhibit multiple conduction mechanisms with series and shunt resistances. Using Thevenin's theorem and the Lambert W function, the terminal current is expressed explicitly as a function of the terminal voltage. Its explicit nature allows higher computational efficiency and makes this model better suited for repetitive simulation applications than conventional implicit models. Additionally, direct analytic differentiation and integration are possible. This alternative model is used to describe the I-V characteristics of real SOI PIN diodes.Artigo Drain current and short channel effects modeling in junctionless nanowire transistors(2013-01-05) TREVISOLI, R. D.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio Pavanello© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.