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- ArtigoUsing the Octagonal Layout Style for MOSFETs to boost the Device Matching in Ionizing Radiation Environments(2020-12-04) PERUZZI , VINICIUS VONO; CRUZ, WILLIAM; SILVA, GABRIEL AUGUSTO DA; SIMOEN, EDDY; CLAEYS, COR; Salvador GimenezThis article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha (α) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird's Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.
- ArtigoUsing the Hexagonal Layout Style for MOSFETs to boost the Device Matching in Ionizing Radiation Environments(2020-08-10) PERUZZI , VINICIUS VONO; CRUZ, WILLIAM; SILVA, GABRIEL AUGUSTO DA; SIMOEN, EDDY; CLAEYS, COR; Salvador GimenezThis paper describes an experimental comparative study of the mismatching between the Diamond (hexagonal gate geometry) and Conventional (rectangular gate shape) n-chan-nel Metal-Oxide-Semiconductor (MOS) Field Effect Transis-tors (MOSFETs), which were manufactured in an 130 nm Sili-con-Germanium Bulk Complementary MOS (CMOS) technol-ogy and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with an alpha () angle equal to 90 ̊ for MOSFETs is capable of re-ducing the device mismatching by at least 17% regarding the electrical parameters studied as compared to the Conventional MOSFET (CnM) counterparts. Therefore, the Diamond layout style can be considered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs.
- ArtigoZero Temperature Coefficient behavior for Ellipsoidal MOSFET(2020) CAMILLO, L. M.; LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GIMENEZ, S. P.
- ArtigoElectrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures(2020-01-05) GALEMBECK, E. H. S.; Salvador GimenezThis paper presents the electrical behavior at high temperature-range of the effects presents in the non-standard gate layout style for MOSFETs, in which they are capable to boost the electrical performance in relation to the one standard rectangular MOSFET (RM) counterpart. These effects are named Longitudinal Corner Effect (LCE) and Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE). In this study, we study the ellipsoidal layout style for MOSFET, taking into account the Bulk technology of CMOS CIs of 180nm from TSMC. This work is based on three-dimensional numerical simulations and we conclude that the LCE and PAMDLE effects are always actives in all temperatures studied (300K-573K) and, consequently, they are capable of boosting the EM electrical performance remarkably in comparison to the RM counterpart (83% for saturation drain current and 86% for the maximum transconductance), regarding that present the same gate areas and bias conditions for a temperature of 573K.
- ArtigoDigital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment(2019-08-25) GALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; Salvador GimenezThis present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.