Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs under Soft Errors
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2017
Autores
Tambara L.A.
Tonfat J.
Santos A.
Kastensmidt F.L.
Medina N.H.
Added N.
Aguiar V.A.P.
Aguirre F.
Silveira M.A.G.
Tonfat J.
Santos A.
Kastensmidt F.L.
Medina N.H.
Added N.
Aguiar V.A.P.
Aguirre F.
Silveira M.A.G.
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IEEE Transactions on Nuclear Science
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TAMBARA, LUCAS ANTUNES; TONFAT, JORGE; SANTOS, ANDRE; LIMA KASTENSMIDT, FERNANDA; MEDINA, NILBERTO H.; ADDED, NEMITALA; AGUIAR, VITOR A. P.; AGUIRRE, FERNANDO; SILVEIRA, MARCILEI A. G.. Analyzing Reliability and Performance Trade-offs of HLS-based Designs in SRAM-based FPGAs under Soft Errors. IEEE Transactions on Nuclear Science, v. 63, p. 1-1, 2017.
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© 1963-2012 IEEE.The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.