Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

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dc.contributor.authorBANIN JÚNIOR, JOSÉ ROBERTO
dc.contributor.authorMORETO, RODRIGO ALVES DE LIMA
dc.contributor.authorSILVA, GABRIEL AUGUSTO DA
dc.contributor.authorTHOMAZ, CARLOS EDUARDO
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-5566-1963
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2021-11-18T18:07:28Z
dc.date.available2021-11-18T18:07:28Z
dc.date.issued2020-11-22
dc.description.abstractThis paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (a) equal to 45, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.
dc.description.firstpage293
dc.description.lastpage306
dc.description.volume106
dc.identifier.citationBANIN JÚNIOR, J. R.; MORETO, R. A. DE L.; SILVA, G. A. DA; THOMAZ, C. E; GIMENEZ, S. P. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 106, p. 293–306, 2021
dc.identifier.doi10.1007/s10470-020-01750-6
dc.identifier.issn0925-1030
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3469
dc.relation.ispartofANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
dc.rightsAcesso Restrito
dc.subjectDiamond MOSFET
dc.subjectHexagonal layout style
dc.subjectDesign
dc.subjectOptimization
dc.subjectOperational transconductance amplifier
dc.subjectiMTGSPICE
dc.subjectSPICE simulation
dc.subjectElectronic evolutionary
dc.subjectOTA
dc.titleMethodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETspt_BR
dc.typeArtigopt_BR
fei.scopus.citations2
fei.scopus.eid2-s2.0-85096366894
fei.scopus.updated2023-10-01
fei.source.urlhttps://link.springer.com/article/10.1007%2Fs10470-020-01750-6
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